The present disclosure relates to the effect of temperature variations on integrated circuit chip power consumption and, particularly, to a system and method for controlling integrated circuit chip temperature and, thereby power consumption, using timing closure-based adaptive frequency scaling.
Total power consumption is a key concern of integrated circuit (IC) chip designers. Those skilled in the art will recognize that there are two components to total power consumption: dynamic power consumption, which refers to power consumption during active operation of the IC chip; and static power consumption, which is refers to power consumption with the IC chip is inactive. More specifically, dynamic power consumption refers to the amount of power required to operate an IC chip and is proportional to the value of the supply voltage (Vdd) squared and to the frequency of operation. Static power consumption refers to the amount of power consumed by the IC chip when it is inactive and is proportional to the value of the supply voltage (Vdd) and to the leakage current. Leakage current refers to the total current that flows through the device when the IC chip is in active. Those skilled in the art will recognize that there is an exponential relationship between the supply voltage and temperature and also an exponential relationship between temperature and the leakage current. Since leakage current and, thereby static power consumption at high temperature is a huge contribution to the total power consumption, techniques are often employed to reduce IC chip temperature when some predetermined maximum temperature is achieved. These techniques can include, for example, reducing the activity level on the IC chip and/or reducing the supply voltage (Vdd) to the IC chip. However, since the activity level and/or supply voltage can only be reduced when the IC chip is operating above a minimum activity level and/or above a minimum supply voltage, respectively, such techniques may not be available to reduce temperature when necessary.